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KM29W32000TS Document Title 4M x 8 Bit NAND Flash Memory Revision History w w w Revision No. History 0.0 1.0 1.1 Initial issue. Data Sheet, 1998 Data Sheet, 1999 1) Added CE don' care mode during the data-loading and reading t .D at Sh a et e 4U . om c FLASH MEMORY Draft Date April 10th 1998 July 14th 1998 April 10th 1999 Remark Preliminary Final Final w w w .D t a S a e h t e U 4 .c m o The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near you. 1 w w w .D at Sh a et e 4U . om c KM29W32000TS 4M x 8 Bit NAND Flash Memory FEATURES * Voltage Supply : 2.7V ~ 5.5V * Organization - Memory Cell Array : (4M + 128K)bit x 8bit - Data Register : (512 + 16)bit x8bit * Automatic Program and Erase - Page Program : (512 + 16)Byte - Block Erase : (8K + 256)Byte - Status Register * 528-Byte Page Read Operation - Random Access : 10s(Max.) - Serial Page Access : 50ns(Min.) * Fast Write Cycle Time - Program time : 250s(typ.) - Block Erase time : 2ms(typ.) * Command/Address/Data Multiplexed I/O port * Hardware Data Protection - Program/Erase Lockout During Power Transitions * Reliable CMOS Floating-Gate Technology - Endurance : 1M Program/Erase Cycles - Data Retention : 10 years * Command Register Operation * 44(40) - Lead TSOP Type II (400mil / 0.8 mm pitch) - Forward Type FLASH MEMORY GENERAL DESCRIPTION The KM29W32000 is a 4M(4,194,304)x8bit NAND Flash Memory with a spare 128K(131,072)x8bit. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. A program operation programs the 528-byte page in typically 250s and an erase operation can be performed in typically 2ms on an 8K-byte block. Data in the page can be read out at 50ns cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command inputs. The on-chip write controller automates all program and erase system functions, including pulse repetition, where required, and internal verify and margining of data. Even the write-intensive systems can take advantage of the KM29W32000 extended reliability of one million program/erase cycles by providing either ECC(Error Correction Code) or real time mapping-out algorithm. These algorithms have been implemented in many mass storage applications and also the spare 16 bytes of a page combined with the other 512 bytes can be utilized by system-level ECC. The KM29W32000 is an optimum solution for large nonvolatile storage application such as solid state storage, digital voice recorder, digital still camera and other portable applications requiring nonvolatility. PIN CONFIGURATION PIN DESCRIPTION VSS CLE ALE WE WP N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C I/O0 I/O1 I/O2 I/O3 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 VCC CE RE R/B SE N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C I/O7 I/O6 I/O5 I/O4 VCCQ Pin Name I/O0 ~ I/O7 CLE ALE CE RE WE WP SE R/B VCC VCCQ VSS N.C Pin Function Data Inputs/Outputs Command Latch Enable Address Latch Enable Chip Enable Read Enable Write Enable Write Protect Spare area Enable Ready/Busy output Power(2.7V ~ 5.5V) Output Butter Power(2.7V ~ 5.5V) Ground No Connection 44(40) TSOP (II) STANDARD TYPE NOTE : Connect all VCC, VCCQ and VSS pins of each device to power supply outputs. Do not leave VCC or VSS disconnected. 2 KM29W32000TS Figure 1. FUNCTIONAL BLOCK DIAGRAM VCC VSS A9 - A21 X-Buffers Latches & Decoders Y-Buffers Latches & Decoders Y-Gating FLASH MEMORY 2nd half Page Register & S/A 32M + 1M Bit NAND Flash ARRAY (512 + 16)Byte x 8192 1st half Page Register & S/A A0 - A7 A8 Command Command Register Y-Gating I/O Buffers & Latches VCCQ VSS I/0 0 I/0 7 CE RE WE Control Logic & High Voltage Generator Global Buffers Output Driver CLE ALE WP Figure 2. ARRAY ORGANIZATION 1 Block(=16 Row) (8K + 256) Byte 32M : 8K Row (=512 Block) 1st half Page Register (=256 Bytes) 2nd half Page Register (=256 Bytes) 1 Page = 528 Bytes 1 Block = 528 B x 16 Pages = (8K + 256) Bytes 1 Device = 528B x 16Pages x 512 Blocks = 33 Mbits 8 bit 16B Column 512B Column Page Register 512Byte I/O 0 ~ I/O 7 16Byte I/O 0 1st Cycle 2nd Cycle 3rd Cycle A0 A9 A17 I/O 1 A1 A10 A18 I/O 2 A2 A11 A19 I/O 3 A3 A12 A20 I/O 4 A4 A13 A21 I/O 5 A5 A14 *X I/O 6 A6 A15 *X I/O 7 A7 A16 *X Column Address Row Address (Page Address) NOTE : Column Address : Starting Address of the Register. 00H Command(Read) : Defines the starting Address of the 1st half of the Register. 01H Command(Read) : Defines the sarting Address of the 2nd half of the Register. * A8 is initially set to "Low" or "High" by the 00H or 01H Command. * X can be High or Low. 3 KM29W32000TS PRODUCT INTRODUCTION FLASH MEMORY The KM29W32000 is a 33Mbit(34,603,008 bit) memory organized as 8192 rows by 528 columns. Spare sixteen columns are located from column address of 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16 cells that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of the 16 pages formed by one NAND structures, totaling 4,224 NAND structures of 16 cells. The array organization is shown in Figure 2. The program and read operations are executed on a page basis, while the erase operation is executed on block basis. The memory array consists of 512 separately or grouped erasable 8K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the KM29W32000. The KM29W32000 has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows systems upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/Os by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus cycle except for Block Erase command which requires two cycles : a cycle for erase-setup and another for erase-execution after block address loading. The 4M byte physical space requires 22 addresses, thereby requiring three cycles for byte-level addressing: column address, low row address and high row address, in that order. Page Read and Page Program need the same three address cycles following the required command input. In Block Erase operation, however, only the two row address cycles are used. Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of the KM29W32000. Table 1. COMMAND SETS Function Sequential Data Input Read 1 Read 2 Read ID Reset Page Program Block Erase Erase Suspend Erase Resume Read Status 1st. Cycle 80h 00h/01h 50h (2) (1) 2nd. Cycle D0h - Acceptable Command during Busy 90h FFh 10h 60h B0h D0h 70h O O O NOTE : 1. The 00H command defines starting address of the 1st half of registers. The 01H command defines starting address of the 2nd half of registers. After data access on the 2nd half of register by the 01H command, the status pointer is automatically moved to the 1st half register(00H) on the next cycle. 2. The 50H command is valid only when the SE(pin 40) is low level. 4 KM29W32000TS PIN DESCRIPTION Command Latch Enable(CLE) FLASH MEMORY The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal. Address Latch Enable(ALE) The ALE input controls the path activation for address and input data to the internal address/data register. Addresses are latched on the rising edge of WE with ALE high, and input data is latched when ALE is low. Chip Enable(CE) The CE input is the device selection control. When CE goes high during a read operation the device is returned to standby mode. However, when the device is in the busy state during program or erase, CE high is ignored, and does not return the device to standby mode. Write Enable(WE) The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse. Read Enable(RE) The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one. Spare Area Enable(SE) The SE input controls the spare area selection when SE is high, the device is deselected the spare area during Read1, Sequential data input and page Program. I/O Port : I/O 0 ~ I/O 7 The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z when the chip is deselected or when the outputs are disabled. Write Protect(WP) The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when the WP pin is active low. Ready/Busy(R/B) The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled. Power Line(VCC & VCCQ) The VCCQ is the power supply for I/O interface logic. It is electrically isolated from main power line(VCC=2.7~5.5V) for supporting 5V tolerant I/O with 5V power supply at VCCQ. 5 KM29W32000TS ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to VSS Temperature Under Bias Storage Temperature Short Circuit Output Current Symbol VIN TBIAS TSTG IOS Rating -0.6 to +7.0 -10 to +125 -65 to +150 5 FLASH MEMORY Unit V C C mA NOTE : 1. Minimum DC voltage is -0.3V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins is VCCQ+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns. 2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED OPERATING CONDITIONS (Voltage reference to GND, TA=0 to 70C) Parameter Supply Voltage Supply Voltage Supply Voltage Symbol VCC VCCQ VSS Min 2.7 2.7 0 Typ. 0 Max 5.5 5.5 0 Unit V V V NOTE : 1. Vcc and VccQ pins are separated each other. DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.) Parameter Sequential Read Operating Current Program Erase Stand-by Current(TTL) Stand-by Current(CMOS) Input Leakage Current Output Leakage Current Input High Voltage Input Low Voltage, All inputs Output High Voltage Level Output Low Voltage Level Output Low Current(R/B) Symbol ICC1 ICC2 ICC3 ISB1 ISB2 ILI ILO VIH VIL VOH VOL IOH=-400A IOL=2.1mA Test Conditions tcycle=80ns, CE=VIL, IOUT=0mA CE=VIH, WP=SE=0V/VCC CE=VCC-0.2, WP=SE=0V/VCC VIN=0 to 5.5V VOUT=0 to 5.5V I/O pins Except I/O pins Vcc=2.7V ~ 3.6V Min 2.0 2.0 -0.3 2.4 8 Typ 10 10 10 10 10 Max 20 20 20 1 50 10 10 VCCQ+0.3 VCC+0.3 0.6 0.4 Vcc=3.6V ~ 5.5V Min 3.0 3.0 -0.3 2.4 8 Typ 15 15 25 10 10 Max 30 30 40 1 50 10 10 VCCQ+0.5 VCC+0.5 0.8 0.4 mA V A mA Unit IOL(R/B) VOL=0.4V 6 KM29W32000TS AC TEST CONDITION (TA=0 to 70C, VCC=2.7V ~ 5.5V unless otherwise noted) Parameter Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load 1 TTL GATE and CL=50pF(3.0V+/-10%),100pF(3.0V~3.6V) Value Vcc=2.7V ~ 3.6V 0.4V to 2.4V 5ns 0.8V and 2.0V FLASH MEMORY Vcc=3.6V ~ 5.5V 0.4V to 3.4V 1 TTL GATE and CL=100pF CAPACITANCE(TA=25C, Vcc=5.0V, f=1.0MHz) Item Input/Output Capacitance Input Capacitance Symbol CI/O CIN Test Condition VIL=0V VIN=0V Min Max 10 10 Unit pF pF NOTE : Capacitance is periodically sampled and not 100% tested. MODE SELECTION CLE H L H L L L L X X X X ALE L H L H L L L X X X(1) X CE L L L L L L L X X X H H H X X X X H X X X X WE RE H H H H H SE X X X X L/H (3) WP X X H H H X X H H L (2) Mode Read Mode Command Input Address Input(3clock) Command Input Address Input(3clock) Write Mode Data Input L/H(3) L/H(3) L/H(3) X X 0V/VCC Sequential Read & Data Output During Read(Busy) During Program(Busy) During Erase(Busy) Write Protect (2) 0V/VCC Stand-by NOTE : 1. X can be VIL or VIH 2. WP should be biased to CMOS high or CMOS low for standby. 3. When SE is high, spare area is deselected. Program/Erase Characteristics Parameter Program Time Number of Partial Program Cycles in the Same Page Block Erase Time Symbol tPROG Nop tBERS Min Typ 0.25 2 Max 1.5 10 10 Unit ms cycles ms 7 KM29W32000TS AC Timing Characteristics for Command / Address / Data Input Parameter CLE Set-up Time CLE Hold Time CE Setup Time CE Hold Time WE Pulse Width ALE Setup Time ALE Hold Time Data Setup Time Data Hold Time Write Cycle Time WE High Hold Time Symbol tCLS tCLH tCS tCH tWP tALS tALH tDS tDH tWC tWH Min 0 10 0 10 25 0 10 20 10 50 15 FLASH MEMORY Max Unit ns ns ns ns ns ns ns ns ns ns ns AC Characteristics for Operation Parameter Data Transfer from Cell to Register ALE to RE Delay(read ID) ALE to RE Delay(Read cycle) CE to RE Delay(ID read) Ready to RE Low RE Pulse Width WE High to Busy Read Cycle Time RE Access Time RE High to Output Hi-Z CE High to Output Hi-Z RE High Hold Time Output Hi-Z to RE Low Last RE High to Busy(at sequential read) CE High to Ready(in case of interception by CE at read) CE High Hold Time(at the last serial read) (3) RE Low to Status Output CE Low to Status Output RE High to WE Low WE High to RE Low Erase Suspend Input to Ready RE access time(Read ID) Device Resetting Time(Read/Program/Erase/after erase suspend) (1) Symbol tR tAR1 tAR2 tCR tRR tRP tWB tRC tREA tRHZ tCHZ tREH tIR tRB tCRY tCEH tRSTO tCSTO tRHW tWHR tSR tREADID tRST Min 150 50 100 20 30 50 15 15 0 100 0 60 - Max 10 100 35 30 20 100 50 +tr(R/B) 35 45 500 35 5/10/500/5 (2) Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s ns s NOTE : 1. If CE goes high within 30ns after the rising edge of the last RE, R/B will not return to VOL. 2. The time to Ready depends on the value of the pull-up resistor tied R/B pin. 3. To break the sequential read cycle, CE must be held high for longer time than tCEH. 8 KM29W32000TS Pointer Operation of KM29W32000 FLASH MEMORY The KM29W32000 has three read modes to set the destination of the pointer. The pointer is set to "A" area by the "00h" command, to "B" area by the "01" command, and to "C" area by the "50h" command. Table 1 shows the destination of the pointer, and figure 2 shows the block diagram of its operations. "A" area (00h plane) "B" area (01h plane) 256 Byte "C" area (50h plane) 16 Byte Table 1. Destination of the pointer 256 Byte Command 00H 01H 50H Pointer position 0 ~ 255 byte 256 ~ 511 byte 512 ~ 527 byte Area 1st half array(A) 2nd half array(B) spare array(C) "A" "B" "C" Internal Page Buffer Pointer select commnad (00h, 01h, 50h) Pointer Figure 2. Block diagram of pointer Operation Example of Pointer Operation programming (1) "A" area program 50h "C" area 00h "A" area 80h Address / Data input 10h "A" area program Address / Data input 01h "A" area "B" area 80h 10h "B" area program Address / Data input 50h "A" area "C" area 80h 10h "C" area program 80h 80h 80h Address / Data input 10h "A" area program Address / Data input 10h "A" area program Address / Data input 10h "C" area program (2) "B" area program 00h (3) "C" area program 00h Table 2. Pointer Status after each operation Operation Program/Erase Pointer status after operation With previous 00H, Device is set to 00H Plane With previous 01H, Device is set to 00H Plane* With previous 50H, Device is set to 50H Plane "00h" Plane("A" area) "00h" Plane("A" area) Reset Power up * 01H command is valid just one time when it is used as a pointer for program/erase. 9 KM29W32000TS System Interface Using CE don' -care. t FLASH MEMORY For a easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal 528byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and reading would provide significant savings in power consumption. Figure 3. Program Operation with CE don' -care. t CLE CE don'-care t CE WE ALE I/O0~7 80H Start Add.(3Cycle) Data Input Data Input 10H (Min. 10ns) tCS CE (Max. 45ns) tCH CE tCEA tREA tWP WE I/O0~7 Timing requirements : If CE is is exerted high during data-loading, tCS must be minimum 10ns and tWC must be increased accordingly. RE out Timing requirements : If CE is is exerted high during sequential data-reading, the falling edge of CE to valid data(tCEA) must be kept greater than 45ns. Figure 4. Read Operation with CE don' -care. t CLE CE don'-care t CE RE ALE R/B tR WE I/O0~7 00H Start Add.(3Cycle) Data Output(sequential) 10 KM29W32000TS * Command Latch Cycle FLASH MEMORY CLE tCLS tCS CE tCLH tCH tWP WE tALS ALE tDS I/O0~7 tALH tDH Command * Address Latch Cycle tCLS CLE tCS CE tWC tWC tWP WE tWH tALS ALE tDS I/O0~7 tDH tWP tWH tWP tALH tDS tDH tDS tDH A0~A7 A9~A16 A17~A21 11 KM29W32000TS * Input Data Latch Cycle tCLH CLE FLASH MEMORY tCH CE tALS ALE tWC tWP WE tDS I/O0~7 tWH tDH tWP tDH tWP tDH tDS tDS DIN 0 DIN 1 DIN 511 * Sequential Out Cycle after Read(CLE=L, WE=H, ALE=L) CE tRC tRP tREA tREH tREA tREA tCHZ* RE tRHZ tRHZ* I/O0~7 tRR R/B Dout Dout Dout tRHZ* NOTES : Transition is measured 200mV from steady state voltage with load. This parameter is sampled and not 100% tested. 12 KM29W32000TS * Status Read Cycle tCLS CLE tCLS tCS CE tCH tWP WE tWHR RE tDS I/O0~7 70H tDH tIR tCSTO tCLH FLASH MEMORY tCHZ* tRSTO tRHZ* Status Output READ1 OPERATION(READ ONE PAGE) CLE tCEH CE tWC WE tWB tAR2 ALE tR RE tRR tRC tRHZ tCRY tCHZ 00h or 01h I/O0~7 A0 ~ A7 A9 ~ A16 A17 ~ A21 Dout N Dout N+1 Dout N+2 Dout N+3 Dout 527 Column Address Page(Row) Address Busy tRB R/B 13 KM29W32000TS READ1 OPERATION(INTERCEPTED BY CE) FLASH MEMORY CLE CE WE tWB tAR2 ALE tR RE tRR I/O0~7 00h or 01h A0 ~ A7 A9 ~ A16 A17 ~ A21 Dout N Dout N+1 Dout N+2 Dout N+3 tCHZ tRC Column Address Page(Row) Address Busy R/B READ2 OPERATION(READ ONE PAGE) CLE CE WE tWB tR tAR2 ALE tRR RE Dout 511+M+1 I/O0~7 50H A0 ~ A7 A9 ~ A16 A17 ~ A21 Dout 511+M 512 Dout 527 R/B M Address A0 ~ A3 :Valid Address A4 ~ A7 :Don't care Selected Row 16 Start address M 14 KM29W32000TS SEQUENTIAL ROW READ OPERATION FLASH MEMORY CLE CE WE ALE RE I/O0~7 00H A0 ~ A7 A9 ~ A16 A17 ~ A21 Dout N Dout N+1 Dout N+2 Dout 527 Dout 0 Dout 1 Dout 2 Dout 527 R/B M Busy M+1 Busy N Output Output PAGE PROGRAM OPERATION CLE CE tWC WE tWB ALE tPROG tWC tWC RE I/O0~7 80H A0 ~ A7 A9 ~ A16 A17 ~ A21 Page(Row) Address Din N Din N+1 Din 527 10H Program Command 70H Read Status Command I/O0 Sequential Data Column Input Command Address 1 up to 528 Byte Data Sequential Input 15 R/B I/O0=0 Successful Program I/O0=1 Error in Program KM29W32000TS BLOCK ERASE OPERATION(ERASE ONE BLOCK) FLASH MEMORY CLE CE tWC WE tWB ALE tBERS tWC RE I/O0~7 60H A9 ~ A16 A17 ~ A21 Block Address DOH 70H I/O0 R/B Auto Block Erase Setup Command Busy Erase Command Read Status Command I/O0=0 Successful Erase I/O0=1 Error in Erase SUSPEND & RESUME OPERATION DURING BLOCK ERASE CLE CE WE tWB ALE RE Block Address tRHW D0H B0H D0H 70H I/O0 I/O0~7 60H A9 ~ A16 A17 ~ A21 tWB tSR Busy R/B Auto Block Erase Setup Command Suspend Program/Read Function are Acceptable Resume I/O0=0 Successful Erase I/O0=1 Error in Erase 16 KM29W32000TS MANUFACTURE & DEVICE ID READ OPERATION FLASH MEMORY CLE CE WE ALE RE tREAID I/O0~7 90H Read ID Command 00H ECH Maker Code E3H Device Code 17 KM29W32000TS DEVICE OPERATION PAGE READ FLASH MEMORY Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00H to the command register along with three address cycles. Once the command is latched, it does not need to be written for the following page read operation. Three types of operations are available : random read, serial page read and sequential read. The random read mode is enabled when the page address is changed. The 528 bytes of data within the selected page are transferred to the data registers in less than 10s(tR). The CPU can detect the completion of this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the registers, they may be read out in 50ns cycle time by sequentially pulsing RE with CE staying low. High to low transitions of the RE clock output the data starting from the selected column address up to the last column address(column 511 or 527 depending on state of SE pin). After the data of last column address is clocked out, the next page is automatically selected for sequential read. Waiting 10s again allows for reading of the selected page. The sequential read operation is terminated by bringing CE high. The way the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of bytes 512 to 527 may be selectively accessed by writing the Read2 command with SE pin low. Addresses A0 to A3 set the starting address of the spare area while addresses A4 to A7 are ignored. Unless the operation is aborted, the page address is automatically incremented for sequential read as in Read1 operation and spare sixteen bytes of each page may be sequentially read. The Read1 command(00H/01H) is needed to move the pointer back to the main area. Figures 3 thru 6 show typical sequence and timings for each read operation. Figure 3. Read1 Operation CLE CE WE ALE R/B RE I/O0~7 00H 01H Start Add.(3Cycle) A0 ~ A7 & A9 ~ A21 Data Output(Sequential) tR (00H Command) 1st half array 2nd half array (01H Command)* 1st half array 2nd half array Data Field Spare Field Data Field Spare Field * After data access on 2nd half array by 01H command, the start pointer is automatically moved to 1st half array (00H) at next cycle. 18 KM29W32000TS Figure 4. Read2 Operation CLE CE WE ALE tR R/B RE I/O0~7 50H Start Add.(3Cycle) A0 ~ A3 & A9 ~ A21 (A4 ~ A7 : Don't Care) 1st half array 2nd half array FLASH MEMORY Data Output(Sequential) Spare Field Data Field Spare Field Figure 5. Sequential Row Read1 Operation tR R/B I/O0~7 tR tR 00H 01H Start Add.(3Cycle) A0 ~ A7 & A9 ~ A21 Data Output 1st Data Output 2nd (528 Byte) Data Output Nth (528 Byte) (SE=H, 00H Command) (SE=L, 00H Command) 1st half array 2nd half array (SE=L, 01H Command) 1st half array 2nd half array 1st half array 2nd half array 1st 2nd 1st 2nd 1st 2nd Nth Nth Nth Data Field Spare Field Data Field Spare Field Data Field Spare Field 19 KM29W32000TS Figure 6. Sequential Read2 Operation(SE=fixed low) tR R/B I/O0~7 FLASH MEMORY tR tR 50H Start Add.(3Cycle) A0 ~ A3 & A9 ~ A21 (A4 ~ A7 : Don't Care) 1st half array Data Output 1st Data Output 2nd (16 Byte) Data Output Nth (16 Byte) 2nd half array 1st 2nd Nth Data Field Spare Field PAGE PROGRAM The device is programmed basically on a page basis, but it does allow multiple partial page programming of a byte or consecutive bytes up to 528, in a single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed ten. The addressing may be done in any random order in a block. A page program cycle consists of a serial data loading period in which up to 528 bytes of data may be loaded into the page register, followed by a nonvolatile programming period where the loaded data is programmed into the appropriate cell. Serial data loading can be started from 2nd half array. About the pointer operation, please refer to the attached technical notes.The serial data loading period begins by inputting the Serial Data Input command(80H), followed by the three cycle address input and then serial data loading. The bytes other than those to be programmed do not need to be loaded. The Page Program confirm command(10H) initiates the programming process. Writing 10H alone without perviously entering the serial data will not initiate the programming process. The internal write controller automatically executes the algorithms and timings necessary for program and verify, thereby freeing the CPU for other tasks. Once the program process starts, the Read Status Register command may be entered, with RE and CE low, to read the status register. The CPU can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O0) may be checked(Figure 7). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status command mode until another valid command is written to the command register. Figure 7. Program & Read Status Operation R/B I/O0~7 tPROG 80H Address & Data Input A0 ~ A7 & A9 ~ A21 528 Byte Data 10H 70H I/O 0 Pass Fail 20 KM29W32000TS BLOCK ERASE FLASH MEMORY The Erase operation can erase on a block(8K Byte) basis. Block address loading is accomplished in two cycles initiated by an Erase Setup command(60H). Only address A13 to A21 is valid while A9 to A12 is ignored. The addresses of the block to be erased to FFH. The Erase Confirm command(D0H) following the block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution ensures that memory contents are not accidentally erased due to external noise conditions. At the rising edge of WE after the erase confirm command input, the internal write controller handles erase, erase-verify and pulse repetition where required. If an erase operation error is detected, the internal verify is halted and erase operation is terminated. When the erase operation is completed, the Write Status Bit(I/O0) may be checked. Figure 8 details the sequence. Figure 8. Block Erase Operation tBERS R/B I/O0~7 60H Address Input(2Cycle) Block Add. : A9 ~ A21 D0H 70H I/O 0 Pass Fail ERASE SUSPEND/ERASE RESUME The Erase Suspend allows interruption during any erase operation in order to read or program data to or from another block of memory. Once an erase process begins, writing the Erase Suspend command (B0H) to the command register suspends the internal erase process, and the R/B signal return to "1". Erase Suspend Status bit will be also set to "1" when the Status Register is read. At this time, blocks other than the suspended block can be read or programmed. The Status Register and R/B operation will function as usual. After the Erase Resume command is written to it, the erase process is restarted from the beginning of the erasing period. The Erase Suspend Status bit and R/B will return to "0". Refer to Figure 9 for operation sequence. Figure 9. Erase Suspend & Erase Resume Operation R/B I/O0~7 60H D0H B0H D0H Block Address input Erase Function Start Erase Function Suspend Erase Function Resume 21 KM29W32000TS READ STATUS FLASH MEMORY The device contains a Status Register which may be read to find out whether program or erase operation is complete, and whether the program or erase operation completed successfully. After writing 70H command to the command register, a read cycle outputs the contents of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer to table 2 for specific Status Register definitions. The command register remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read cycle, a read command(00H or 50H) should be given before sequential page read cycle. Table2. Status Register Definition SR I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 Erase Suspend Device Operation Write Protect Reserved for Future Use Status Program / Erase Definition "0" : Successful Program / Erase "1" : Error in Program / Erase "0" "0" "0" "0" "0" : Erase in Progress / Completed "1" : Suspended "0" : Busy "0" : Protected "1" : Ready "1" : Not Protected READ ID The device contains a product identification mode, initiated by writing 90H to the command register, followed by an address input of 00H. Two read cycles sequentially output the manufacture code(ECH), and the device code (E3H) respectively. The command register remains in Read ID mode until further commands are issued to it. Figure 9 shows the operation sequence. Figure 9. Read ID Operation CLE tCR CE WE tAR1 ALE RE I/O0~7 tREADID 90H 00 Address. 1 cycle ECH Maker code E3H Device code 22 KM29W32000TS RESET FLASH MEMORY The device offers a reset feature, executed by writing FFH to the command register. When the device is in Busy state during random read, program or erase modes, the reset operation will abort these operation. The contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. Internal address registers are cleared to "0"s and data registers to "1"s. The command register is cleared to wait for the next command, and the Status Register is cleared to value C0H when WP is high. Refer to table 3 for device status after reset operation. If the device is already in reset state a new reset command will not be accepted to by the command register. The R/B pin transitions to low for tRST after the Reset command is written. Reset command is not necessary for normal operation. Refer to Figure 10 below. Figure 10. RESET Operation tRST R/B I/O0~7 FFH Table3. Device Status After Power-up Operation Mode Read 1 After Reset Waiting for next command DATA PROTECTION The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 2V. WP pin provides hardware protection and is recommended to be kept at VIL during power-up and power-down as shown in Figure 8. The two step command sequence for program/erase provides additional software protection. Figure 8. AC Waveforms for Power Transition ~ 2.5V ~ 2.5V VCC WP 23 High KM29W32000TS READY/BUSY FLASH MEMORY The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command register or random read is begin after address loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. An appropriate pull-up resister is required for proper operation and the value may be calculated by following equation. VCC VCC(Max.) - VOL(Max.) Rp = R/B open drain output where IL is the sum of the input currents of all devices tied to the R/B pin. IOL + IL = Note* 8mA + IL GND Device Note* KM29W32000A : 5.1V When Vcc=3.6~5.5V 3.2V When Vcc=2.7~3.6V 24 KM29W32000TS PACKAGE DIMENSIONS 44(40) LEAD PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(II) 44(40) - TSOP2 - 400F FLASH MEMORY Unit :mm/Inch 0~8 0.25 0.010 TYP #44(40) #23(21) 0.45~0.75 0.018~0.030 11.760.20 0.4630.008 10.16 0.400 0.50 0.020 #1 #22(20) +0.10 0.15 -0.05 0.006 -0.002 +0.004 18.410.10 0.7250.004 1.000.10 0.0390.004 1.20 Max. 0.047 18.81 Max. 0.741 0.10 MAX 0.004 0.05 Min. 0.002 ( 0.805 ) 0.032 0.350.10 0.0140.004 0.80 0.0315 25 |
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